Random access memory (RAM) device include an array of storage circuits (cells), each having two stable states for storing a binary bit (digit) of data (information). Also, random access memory devices include decoding circuitry for indexing the various cells. In addition, random access memory devices include circuitry for writing data into indexed cell(s); and, circuitry for reading stored data out of indexed cell(s).
Unfortunately, because of various propagation and switching delays, it takes a period of time to write new information into and read stored information out of random access memory devices. Further, since writing is destructive, with most devices, once a write cycle is began, it can not be prematurely abandoned, with confidence that the data has not been corrupted.
To improve system performance, often times, a relatively large, but relatively slow, main memory is supplemented by a relatively small, but relatively fast, cache memory, to store frequently used data. In one embodiment (referred to as direct mapped cache memory), the cache memory is divided into two portions, respectively referred to as a data portion and a tag portion. Each of the portions is configured to be indexed by the least significant bits (only) of an address used to index the main memory. In addition, the data portion is configured to store at the indexed location the same word (bits) of data which is stored at the indexed location of the main memory; and, the tag portion is configured to store at the indexed location the other (the most significant) bits of the main memory address, which are referred to as the tag.
Included with the cache memory is a comparator, configured to compare each tag read from the tag portion of the cache memory with the tag portion of the (current) address. Also included with the cache memory is some control circuitry. The control circuitry is configured to, initially, clear (zero) the tag portion of the cache memory. In addition, the control circuitry is configured such that when a word of data is read, the tag stored at the indexed location of the tag portion of the cache memory is read and compared with the tag portion of the (current) address. If the two tags are different, referred to as a cache miss, the required word of data is not currently stored in the data portion of the cache memory. In that case, the circuitry reads the word of data from the (relatively slow) main memory. In addition, the circuitry stores the word of data (read from the main memory) at the indexed location of the data portion of the cache memory and stores the current tag at the indexed location of the tag portion of the cache memory. If the two tags are the same, referred to as a cache hit, the required word of data is currently stored in the data portion of the cache memory. In that case, the circuitry reads the word of data from the (data portion of the) (relatively fast) cache memory.
Usually, the control circuitry is, in addition, configured to do what is referred to as a write through. More specifically, when a word of data is written, the tag stored at the indexed location of the tag portion of the cache memory is read and compared with the tag portion of the (current) address. If the two tags are the same (and, usually, only if the two tags are the same), the circuitry stores the word of data at the indexed location of the data portion of the cache memory. Of course, in either case, the word of data is stored at the indexed location of the main memory. (Usually, the address and the data word are stored so that another operation can be performed while the word of data is being stored in the (relatively slow) main memory.)
It is important to note that, absent some means for, safely, prematurely abandoning a write cycle, a write to the cache memory requires two full cycles. Specifically, a read cycle (to read the tag stored at the indexed location of the tag portion of the cache memory and compare it with the tag portion of the (current) address) must be completed before a write cycle (to store the word of data at the indexed location of the data portion of the cache memory) may be begun.
A synchronous, random access memory device having conditional write means is disclosed in the Integrated Device Technology Incorporated preliminary applications note which is entitled CMOS Synchronous RAM 64K (64K by one-bit), which is designated IDT7l50lS, and which is dated December 1987. The device, which is illustrated in FIG. 1 of the drawing generally designated by the number 100, is shown to include a number of pipeline registers (flip-flops) configured to store the states of a number of externally-generated signals. More specifically, device 100 is shown to include an address register 102, that employs sixteen D-type flip-flops (which, for clarity, are not shown). The flip-flops of address register 102 are configured each with the data input connected to a respective line of a sixteen-line address bus 104, to receive a respective one of sixteen externally-generated indexing signals, with the flip-flop clock input connected to a line 106 to receive an externally-generated clocking signal, and with the flip-flop data output connected to a respective line of a sixteen-line bus 108. To store the state of an externally-generated (active-low) chip-selecting signal, another D-type flip-flop (register) 112 is included, which is configured with the flip-flop data input connected to a line 114 to receive the externally-generated chip-selecting signal, with the flip-flop clock input connected to line 106 to receive the externally-generated clocking signal, and with the flip-flop data output connected to a line 118. A D-type flip-flop 122 (register) is included to store the state of an externally-generated signal that represents a bit of data. Flip-flop 122 is configured with the flip-flop data input connected to a line 124 to receive the externally-generated data signal, with the flip-flop clock input connected to line 106 to receive the externally-generated clocking signal, and with the flip-flop data output connected to a line 128. Finally, to store the state of an externally-generated (active-low) write-enabling (read/write) signal, a D-type flip-flop (register) 132 is included, which is configured with the flip-flop data input connected to a line 134 to receive the externally-generated write-enabling signal, with the flip-flop clock input connected to line 106 to receive the externally-generated clocking signal, and with the flip-flop data output connected to a line 138.
Further, device 100 is shown to include a 64K by one array 140 of random access memory cells (and associated control logic). Array 140 is configured with the (sixteen) array address inputs each connected to a respective one of the sixteen lines of bus 108, with the (active-low) array chip-select input connected to line 118, with the array data input connected to line 128, with the (active-low) array write-enable (read/write) input connected to line 138 and with the array data output connected to a line 148.
Finally, device 100 is shown to include a pipeline register (flip-flop) configured, with another flip-flop, a pair of associated gates, and a buffer, to store the state of the data signal generated by array 140 and to develop an output signal. More specifically, to store the state of the array 140 data signal, device 100 is shown to include a D-type flip-flop (register) 150, which is configured with the flip-flop data input connected to line 148 to receive the data-output signal developed by array 140, with the flip-flop clock input connected to a line 106 to receive the externally-generated clocking signal, and with the flip-flop data output connected to a line 158. To buffer the flip-flop 150 stored data-output signal, a buffer 160 is included, which is configured with the buffer data input connected to line 158 to receive the stored data-output signal, with the buffer enable input connected to a line 164 to receive an output-enabling signal, and with the buffer data output connected to a line 168. A two-input AND gate 170, which has both a true (non-negated) input and a negated input is included. Gate 170 is configured with the negated gate input connected to line 118 to receive the stored chip-selecting signal, with the true gate input connected to line 138 to receive the stored write-enabling signal, and with the gate output connected to a line 178. A D-type flip-flop (register) 180 is included, which is configured with the flip-flop data input connected to line 178 to receive the gate 170 developed signal, with the flip-flop clock input connected to line 106 to receive the externally-generated clocking signal, and with the flip-flop data output connected to a line 188. Finally, included is another two-input AND gate 190, which also has both a true (non-negated) input and a negated input. Gate 190 is configured with the gate true input connected to line 188 to receive the flip-flop 180 developed signal, with the gate negated input connected to a line 194 to receive an externally-generated output-enabling signal, and with the gate output connected to line 164, upon which the gate develops the buffer 160 output-enabling signal. (Of course, an inverter can be employed to convert a true (non-negated) input into a negated input.)
With device 100, a write cycle can be prematurely abandoned with confidence that the data stored in the device has not been corrupted, by suitably altering the state of the write-enabling signal externally-generated on line 134 (or the chip-selecting signal externally-generated on line 114), before the time marked by the clocking signal externally-generated on line 106. Unfortunately, however, device 100 requires more than one cycle for a read operation. (During a first cycle, the externally-generated signals (including the address signals externally-generated on bus 104) are stored in the input registers (including register 102). During the next (second) cycle, the state of the data signal developed by random access memory array 140 on line 148 is stored in flip-flop (register) 150. Only late in the second cycle, at a time following the time marked by the clocking signal externally-generated on line 106 does the state of the signal developed by buffer 160 on line 168 represent the data stored in array 140 at the indexed location.) In addition, device 100 requires a special clocking signal (externally-generated on line 106).